Floorplanning with abutment constraints based on corner block list

被引:6
作者
Ma, YC [1 ]
Hong, XL
Dong, SQ
Cai, YC
Cheng, CK
Gu, J
机构
[1] Tsinghua Univ, Dept Comp Sci & Technol, Beijing 100084, Peoples R China
[2] Univ Calif San Diego, Dept Comp Sci & Engn, La Jolla, CA 92093 USA
[3] Sci & Technol Univ Hong Kong, Dept Comp Sci, Hong Kong, Hong Kong, Peoples R China
基金
美国国家科学基金会;
关键词
VLSI floorplan; abutment constraint; simulated annealing algorithm; corner block list (CBL);
D O I
10.1016/S0167-9260(01)00022-0
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Corner Block List (CBL) was recently proposed as an efficient representation of general rectangle packing: different from other topological representations, CBL needs a smaller amount of encoding storage and linear time computation effort to generate each placement configuration. To extend its applicability to simple rectangle packings, this paper addresses the problem of handling abutment constraints in the context of the CBL representation. We can obtain the abutment information by scanning the intermediate solutions represented by CBL in linear time during the simulated annealing process and fix the CBL by the heuristic method in case the constraints are violated. A novel penalty function is derived to measure the violation of the abutment constraints and help to ensure all the constraints are satisfied at the end of the annealing process. The experimental results are demonstrated by several examples of MCNC benchmarks and the performance shows the effectiveness of the proposed method. (C) 2001 Elsevier Science B.V. All rights reserved.
引用
收藏
页码:65 / 77
页数:13
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