Design and Analysis of Dual Modulus Prescaler Circuit for Frequency Synthesizer

被引：0
|
作者：
Saw, Suraj Kumar [1 ]
Maiti, Madhusudan [1 ]
Meher, Preetisudha [1 ]
机构：
[1] Natl Inst Technol, VLSI Design Lab, Dept Elect & Commun Engn, Papum Pare 79112, Arunachal Prade, India
来源：
2019 IEEE INTERNATIONAL SYMPOSIUM ON SMART ELECTRONIC SYSTEMS (ISES 2019) | 2019年
关键词：
Prescaler; Phase Locked Loop; Frequency Synthesizer; Voltage Controlled Oscillator; Phase Noise; PHASE-LOCKED LOOP; DIVIDE-BY-N;
D O I：
10.1109/iSES47678.2019.00049
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Our proposed circuits incorporated with dual modulus circuit with additional Logic along with two D latches, which can divide in a ratio of (2/3) by using Current mode Logic (CML) based topology which reduces the delay and consumes very low power consumption of 339.5 mu W by applying a supply voltage of 1.2V which can drive high frequency up to 20Ghz, with a phase noise and output noise of -128.04dBc/Hz and -137.61dB @ 1 MHz offset respectively.
引用
收藏
页码：185 / 188
页数：4
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