A Parallel BP Neural Network Based on the FPGA

被引：1

作者：

Guo Yu-Hui ^{[1
]}

Zhou De-Tai ^{[1
]}

Qian Xiang-Ping ^{[2
]}

Zeng Xian-Qiang ^{[1
]}

机构：

[1] Chinese Acad Sci, Inst Modern Phys, 509 Nanchang Rd, Lanzhou, Gansu, Peoples R China

[2] Lanzhou Univ, Sch Nucl Sci & Technol, Lanzhou, Gansu, Peoples R China

来源：

MEASUREMENT TECHNOLOGY AND ITS APPLICATION, PTS 1 AND 2 | 2013年 / 239-240卷

关键词：

Neural network; Field programmable gate array(FPGA); Back Propagation algorithm; Parallel architecture; System On Programmable Chip(SOPC);

D O I：

10.4028/www.scientific.net/AMM.239-240.1541

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper, with the analysis of BP neural network learning and execution algorithm on single computer unit, a parallel neural network on many computer units is constructed, a system on programmable chip based on FPGA and uClinux is provided. Because it's flexibility and reliability, this parallel neural network can be widely used where there is a large quantity of data to be processed. In addition to it, the system based on the SOPC has good versatility and easy to transplant because the reconfiguration of the hardware logic and software system.

引用

页码：1541 / +

页数：2

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