A Wide Tuning Range (1 GHz-to-15 GHz) Fractional-N All-Digital PLL in 45nm SOI

被引：6
|
作者：
Rylyakov, Alexander [1 ]
Tierno, Jose [1 ]
English, George [2 ]
Sperling, Michael [2 ]
Friedman, Daniel [1 ]
机构：
[1] IBM Corp, TJ Watson Res Ctr, Yorktown Hts, NY USA
[2] IBM Corp, Poughkeepsie, NY USA
来源：
PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2008年
关键词：
D O I：
10.1109/CICC.2008.4672113
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An all static CMOS (45nm SOI) all-digital fractional-N PLL has a wide tuning range (from 0.84 GHz to 13.3 GHz, at 1.0V, 65 degrees C) and supports a broad range of multiplication factors (up to 1,000x) and reference clock speeds (from 2 MHz to 1 GHz). At 125 degrees C the period jitter of the 4.12 GHz clock (206 MHz reference) is 1.1ps rms (11.4ps pp) at 1.3V (52.4mW), and 2.2ps rms, (22.7ps pp) at 0.7V (9.7mW). The area of the PLL is 175 mu m x 160 mu m.
引用
收藏
页码：431 / +
页数：2
相关论文
共 50 条
  • [41] A 0.5V 1.6mW 2.4GHz Fractional-N All-Digital PLL for Bluetooth LE with PVT-Insensitive TDC using Switched-Capacitor Doubler in 28nm CMOS
    Kuo, Feng-Wei
    Pourmousavian, Seyednaser
    Siriburanon, Teerachot
    Chen, Ron
    Cho, Lan-chou
    Jou, Chewn-Pu
    Hsueh, Fu-Lung
    Staszewski, Robert Bogdan
    2017 SYMPOSIUM ON VLSI CIRCUITS, 2017, : C178 - C179
  • [42] A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS
    Pourmousavian, Naser
    Kuo, Feng-Wei
    Siriburanon, Teerachot
    Babaie, Masoud
    Staszewski, Robert Bogdan
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53 (09) : 2572 - 2583
  • [43] A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS
    Pellerano, Stefano
    Madoglio, Paolo
    Palaskas, Yorgos
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (12) : 3422 - 3433
  • [44] A 1.56GHz Wide-Tuning All Digital FBAR-Based PLL in 0.13μm CMOS
    Hu, Julie R.
    Ruby, Richard C.
    Otis, Brian P.
    IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010, 2010,
  • [45] A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
    Elkholy, Ahmed
    Anand, Tejasvi
    Choi, Woo-Seok
    Elshazly, Amr
    Hanumolu, Pavan Kumar
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015, 50 (04) : 867 - 881
  • [46] A 1.75 mW 1.1 GHz Semi-Digital Fractional-N PLL With TDC-Less Hybrid Loop Control
    Sun, Yuanfeng
    Zhang, Zhuo
    Xu, Ni
    Wang, Min
    Rhee, Woogeun
    Oh, Tae-Young
    Wang, Zhihua
    IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2012, 22 (12) : 654 - 656
  • [47] A 1pJ/bit 10Gbps Optical Carrier-Injection Ring Modulator and All-Digital Driver Circuit in 45nm SOI
    Gupta, Kanchan
    2015 IEEE DALLAS CIRCUITS AND SYSTEMS CONFERENCE (DCAS), 2015,
  • [48] 12.2 GHz All-digital PLL with Pattern Memorizing Cells for Low Power/low Jitter using 65 nm CMOS Process
    Lee, Sanggeun
    Oh, Taehyoun
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2021, 21 (02) : 152 - 156
  • [49] A Compact 3.9-4.7 GHz, 0.82 mW All-Digital PLL with 543 fs RMS Jitter in 28 nm CMOS
    Levinger, R.
    Shumaker, E.
    Levi, R.
    Machluf, N.
    Levin, S.
    Farber, A.
    Horovitz, G.
    2019 IEEE 19TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF), 2019, : 321 - 324
  • [50] A 2.7-to-4.3GHz, 0.16psrms-Jitter,-246.8dB-FOM, Digital Fractional-N Sampling PLL in 28nm CMOS
    Gao, Xiang
    Burg, Olivier
    Wang, Haisong
    Wu, Wanghua
    Tu, Cao-Thong
    Manetakis, Konstantinos
    Zhang, Fan
    Tee, Luns
    Yayla, Mustafa
    Xiang, Sining
    Tsang, Randy
    Lin, Li
    2016 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2016, 59 : 174 - U236
12345