A Wide Tuning Range (1 GHz-to-15 GHz) Fractional-N All-Digital PLL in 45nm SOI

被引：6
|
作者：
Rylyakov, Alexander [1 ]
Tierno, Jose [1 ]
English, George [2 ]
Sperling, Michael [2 ]
Friedman, Daniel [1 ]
机构：
[1] IBM Corp, TJ Watson Res Ctr, Yorktown Hts, NY USA
[2] IBM Corp, Poughkeepsie, NY USA
来源：
PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2008年
关键词：
D O I：
10.1109/CICC.2008.4672113
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An all static CMOS (45nm SOI) all-digital fractional-N PLL has a wide tuning range (from 0.84 GHz to 13.3 GHz, at 1.0V, 65 degrees C) and supports a broad range of multiplication factors (up to 1,000x) and reference clock speeds (from 2 MHz to 1 GHz). At 125 degrees C the period jitter of the 4.12 GHz clock (206 MHz reference) is 1.1ps rms (11.4ps pp) at 1.3V (52.4mW), and 2.2ps rms, (22.7ps pp) at 0.7V (9.7mW). The area of the PLL is 175 mu m x 160 mu m.
引用
收藏
页码：431 / +
页数：2
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