Cell designs for self-timed FPGAs

被引：14

作者：

Traver, C ^{[1
]}

Reese, RB ^{[1
]}

Thornton, MA ^{[1
]}

机构：

[1] Union Coll, Dept Elect Engn & Comp Sci, Schenectady, NY 12308 USA

来源：

14TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS | 2001年

关键词：

self-timed; asynchronous; programmable;

D O I：

10.1109/ASIC.2001.954693

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A self-timed programmable architecture used for the implementation of Phased Logic (PL) systems is described. PL systems are automatically translated from clocked designs and result in self-timed circuits that are insensitive to delays between gates. The target implementation is a self-timed FPGA architecture composed of PL gates. A PL gate design based on a 4-input lookup table is presented. Power and performance estimates of two designs are given and are compared to their clocked counterparts.

引用

页码：175 / 179

页数：5

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