A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP Technology

In advanced technology nodes, static power consumption dominates system power in applications that do not operate at high frequency. SRAM leakage is a major component of static power consumption of a SOC. In this paper, we propose a 81nW ultra low power error amplifier to control retention leakage of 4Mb SRAM array. The overall memory subsystem leakage power reduces by 50% from no retention case and 33% from the conventional retention solution at TT (25 degrees C). At FNSP (140 degrees C) leakage power reduces by 75% from no retention & 69% from conventional solution. Monte Carlo analysis shows the 3 sigma variations are within guard band limits.