Enhanced switched-current comparator

被引：4

作者：

Worapishet, A ^{[1
]}

Hughes, JB

Toumazou, C

机构：

[1] Mahanakorn Univ Technol, Dept Telecommun Engn, Bangkok 10530, Thailand

[2] Univ London Imperial Coll Sci Technol & Med, Dept Elect & Elect Engn, London SW7 2BT, England

来源：

ELECTRONICS LETTERS | 1999年 / 35卷 / 10期

关键词：

Computer simulation - Electric network analysis - Switching circuits;

D O I：

10.1049/el:19990580

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Practical techniques for accuracy and speed enhancement in switched-current (ST) comparators are presented. Both techniques require minimum added complexity and, more importantly, possess no performance penalty for the comparator in terms of noise and power. Extensive simulations indicate an enhanced SI comparator with an improvement in resolution of > 2.5bit/s and a speed increase of a factor of 1.35 over those of the basic SI comparator. This makes it feasible for the implemention of an SI comparator with > 8.5bit resolution at an operating speed of > 270MHz for a power consumption of < 1.7mW.

引用

页码：767 / 768

页数：2