Advanced metallization processes integration as manufacturing worthy solutions for >10: 1 aspect ratio mid-process TSV

被引：0

作者：

Mourier, Thierry ^{[1
]}

Gottardi, Mathilde ^{[1
]}

Ribiere, Celine ^{[1
]}

Romero, Gilles ^{[2
]}

Minoret, Stephane ^{[1
]}

Philip, Pierre-Emile ^{[1
]}

机构：

[1] CEA, LETI, MINATEC Campus,17 Rue Martyrs, F-38054 Grenoble, France

[2] STMicroelectronics, 850 Rue Jean Monnet, F-38926 Crolles, France

来源：

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：141 / 143

页数：3

共 2 条

[1] Full 300 mm Electrical Characterization of 3D Integration Using High Aspect Ratio (10:1) Mid-Process Through Silicon Vias
Gaillard, F.
Mourier, T.
Religieux, L.
Bouchu, D.
Ribiere, C.
Minoret, S.
Gottardi, M.
Romero, G.
Mevellec, V.
Aumont, C.
2015 IEEE 17TH ELECTRONICS PACKAGING AND TECHNOLOGY CONFERENCE (EPTC), 2015,
[2] High Aspect Ratio∼10 TSV Via-last-from-back Process Development and integration
Wang, Xiangyu
Li, Hongyu
2018 IEEE 20TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2018, : 747 - 752