Three-Phase Cascaded Delayed Signal Cancellation PLL for Fast Selective Harmonic Detection

被引：209

作者：

Wang, Yi Fei ^{[1
]}

Li, Yun Wei ^{[1
]}

机构：

[1] Univ Alberta, Dept Elect & Comp Engn, Edmonton, AB T6G 2V4, Canada

来源：

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS | 2013年 / 60卷 / 04期

关键词：

Active power filter (APF); delayed signal cancellation (DSC); harmonic detection; phase-locked loop (PLL); selective harmonic compensation; ACTIVE POWER FILTER; DISCRETE FOURIER-TRANSFORM; GRID SYNCHRONIZATION; LOCKED LOOP; FREQUENCY; IMPLEMENTATION; COMPENSATION; INTEGRATORS; ROBUST; SYSTEM;

D O I：

10.1109/TIE.2011.2162715

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Fast and accurate selective harmonic detection has crucial value for many power system harmonic compensation systems. The existing detection methods are known to have a few drawbacks, such as long delay time, sensitivity to grid frequency variation, and difficulty to achieve zero steady-state error. In order to overcome these drawbacks, this paper proposes a selective harmonic detection system based on the three-phase cascaded delayed signal cancellation phase-locked loop. The system can be flexibly configured to detect any individual harmonic from the source with various background harmonics. It also features very short transient and excellent adaptability under small and considerable frequency variations, as verified by comprehensive experimental results. Finally, this paper provides guidance on how to tailor the detection system for different applications and a solution to address the practical implementation issues.

引用

页码：1452 / 1463

页数：12

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