Design of Schmitt Trigger Logic Gates Using DTMOS for Enhanced Electromagnetic Immunity of Subthreshold Circuits

被引：13

作者：

Kim, Kyungsoo ^{[1
]}

Kim, SoYoung ^{[1
]}

机构：

[1] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon 440746, South Korea

来源：

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY | 2015年 / 57卷 / 05期

基金：

新加坡国家研究基金会;

关键词：

Digital circuits; electromagnetic interference (EMI); hysteresis; immunity; Schmitt trigger; EMI SUSCEPTIBILITY;

D O I：

10.1109/TEMC.2015.2427992

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents subthreshold digital circuit design and optimization method using Schmitt trigger logic gates for enhanced electromagnetic immunity. The proposed Schmitt trigger logic gates are based on a buffer design using dynamic threshold-voltage MOS for low-power operation. By expanding the Schmitt trigger to NAND/NOR gate, we can dramatically improve the noise immunity with much lower switching power consumption and significant area reduction compared with CMOS Schmitt triggers, at the expense of a slight increase in delay. Not only for the gate level, but also the circuit level immunity improvement is verified with ISCAS 85 benchmark. In addition, we propose a parameter to determine the optimal noise immunity considering the trade-off between immunity and performance. By using the proposed parameter, optimal hysteresis can be chosen for the reasonable performance deterioration.

引用

页码：963 / 972

页数：10

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