Combining Axial and Radial Nanowire Heterostructures: Radial Esaki Diodes and Tunnel Field-Effect Transistors

被引:63
作者
Dey, Anil W. [1 ]
Svensson, Johannes [1 ]
Ek, Martin [2 ]
Lind, Erik [1 ]
Thelander, Claes [1 ]
Wernersson, Lars-Erik [1 ]
机构
[1] Lund Univ, S-22100 Lund, Sweden
[2] Lund Univ, Div Polymer & Mat Chem, S-22100 Lund, Sweden
基金
瑞典研究理事会;
关键词
Three-dimensional (3D) nanowire device architecture; radial tunnel field-effect transistor; TFET; nanowire; InAs; GaSb; broken gap; PERFORMANCE;
D O I
10.1021/nl4029494
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit (Radosavljevic et al., IEEE Int. Devices Meeting 2009, 1-4 and Cho et al., IEEE Int. Devices Meeting 2011, 15.1.1-15.1.4). The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Moreover, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties (del Alamo, Nature 2011, 479, 317-323, and Liao et al., Nature 2010, 467, 305-308). In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a constant drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects; however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require additional chip area. The use of a core shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addition to design advantages of a radial transistor architecture, we in this work illustrate the benefit in terms of drive current per unit chip area and compare the experimental data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the electrical data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. Our data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, J(peak) = 2310 kA/cm(2), than the maximum peak current of axial GaSb/InAs(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities J(peak) = 1210 kA/cm(2),
引用
收藏
页码:5919 / 5924
页数:6
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