Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part I-Modeling and Simulation Method

被引：34

作者：

Jiang, Xiaobo ^{[1
]}

Wang, Runsheng ^{[1
]}

Yu, Tao ^{[1
]}

Chen, Jiang ^{[2
]}

Huang, Ru ^{[1
]}

机构：

[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China

[2] Peking Univ, Dept Elect, Beijing 100871, Peoples R China

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2013年 / 60卷 / 11期

关键词：

Auto-correlation function; cross-correlation; line-edge-roughness (LER); line-width-roughness (LWR); modeling; variability; INTRINSIC PARAMETER FLUCTUATIONS; VARIABILITY; MOSFETS; DECANANOMETER;

D O I：

10.1109/TED.2013.2283518

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the correlation between line-edge roughness (LER) and line-width roughness (LWR) is investigated. Based on the characterization methodology of auto-correlation functions (ACF), a new theoretical model of LWR is proposed, which indicates that the LWR ACF is composed of two parts: one involves LER information; the other involves the cross-correlation of the two edges. Additional characteristic parameters for LER/LWR are proposed to represent the missing cross-correlation information in conventional approaches of LER/LWR description, other than LER/LWR amplitude and auto-correlation length. An improved simulation method for correlated LERs is also proposed, which can provide helpful guidelines for the characterization, modeling, and the optimization of LER/LWR in nanoscale CMOS technology. The experimental results and device simulation results are discussed in detail in the part II of this paper.

引用

页码：3669 / 3675

页数：7

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