A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic

This paper presents a 9-bit 400-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with hybrid arranged capacitor array. High-speed operation is achieved by introducing a redundant weighting method into the hybrid arranged SAR CDAC and using a fast control logic which shorten the critical path. By using a custom-designed unit capacitor which minimizes top plate parasitic capacitance, the SAR ADC can realize a wide input range of 1.6 V-diff,V-p-p at 1-V reference voltage. At 400 MS/s sampling rate, the ADC achieves an SNDR of 52.47 dB and consumes 1.19 mW, resulting in a figure of merit (FOM) of 7.8 fJ/conversion-step. The ADC is fabricated in a 28 nm CMOS technology and its core occupies an active area of 171 mu m x 112 mu m.