Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications

A novel "16 transistor" (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is derived based on carry dependent sum implementation approach. The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1-bit FA circuits reported till date. All the comparisons are done at post layout level with respect to the DMs under consideration. The proposed 1-bit FA dissipates an average power of 2.118 W, with a delay of 606 ps, with an area of 33.1 mu m(2), resulting in a PDP of 1.28 fJ. This power and hence the PDP is the lowest of all, ever reported till date. In this comparative study a common test bench with a supply voltage V-DD = 1.2 V, input signal frequency f(in) = 200 MHz is used. This 1-bit FA is designed and implemented using Cadences' 90 nm "generic-process-design-kit" (GPDK).