Advanced Nanometer Technology Analog Layout Retargeting for Lithography Friendly Design

被引：0
|
作者：
Dong, Xuan [1 ]
Zhang, Lihong [1 ]
机构：
[1] Mem Univ, Fac Engn & Appl Sci, Dept Elect & Comp Engn, St John, NF, Canada
来源：
2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2016年
关键词：
lithographic effects; spot defect; analog layout retargeting;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper a yield-aware template-based analog layout retargeting methodology for lithography-friendly nanometer technology designs is proposed. The yield performance is evaluated by probability of failure (POF), which is independent of any specific defect size, and is improved by wire-widening and wire-shifting inside the retargeting process. The non-traditional design rules, which are becoming prominent in the advanced nanometer technologies, have been tackled in the template. The retargeting flow is demonstrated from 0.18um CMOS technology to 65nm CMOS technology with significant yield improvement.
引用
收藏
页码：1262 / 1265
页数：4
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