Floating gate memories for pulse-stream neural networks

被引：2
作者：
Buchan, LW
Murray, AF
Reekie, HM
机构：
[1] Department of Electrical Engineering, University of Edinburgh, Edinburgh, EH9 3JL, Mayfield Road
来源：
ELECTRONICS LETTERS | 1997年 / 33卷 / 05期
关键词：
neural networks; VLSI;
D O I：
10.1049/el:19970251
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Floating gate memory cells fabricated in a standard, low-voltage CMOS process have been evaluated experimentally. A circuit has been proposed which allows target voltages on thr floating gate to be established. An application of this circuit is demonstrated in the rapid down-loading of weight sets in a pulse-stream neural network for 'chip-in-the-loop' training.
引用
收藏
页码：397 / 399
页数：3
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