Impact of barrier thickness on Analog, RF and Linearity performance of nanoscale DG heterostructure MOSFET

被引：21
作者：
Biswas, Kalyan [1 ]
Sarkar, Angsuman [2 ]
Sarkar, Chandan Kumar [3 ]
机构：
[1] MCKV Inst Engn, ECE Dept, Liluah, WB, India
[2] Kalyani Govt Engn Coll, ECE Dept, Kalyani, WB, India
[3] Jadavpur Univ, ETCE Dept, Nano Device Simulat Lab, Kolkata, WB, India
来源：
SUPERLATTICES AND MICROSTRUCTURES | 2015年 / 86卷
关键词：
Heterostructure MOSFET; Analog/RF performance; Linearity; Barrier thickness; III-V MOSFET; Double gate; GATE; LENGTH; CMOS;
D O I：
10.1016/j.spmi.2015.06.047
中图分类号：
O469 [凝聚态物理学];
学科分类号：
070205 ;
摘要：
In this work, we have analyzed the Analog, RF and Linearity performance of InP/InGaAs hetero-junction MOSFET using TCAD device simulation. A detailed investigation of the impact of barrier layer thickness on different Analog, RF and Linearity performance of an InGaAs/InP heterostructure DG MOSFET is carried out. A thorough analysis of the key figure-of-merits such as transconductance (g(m)), Output resistance (R-0), gate capacitance, cutoff frequency (f(T)), maximum frequency of oscillation (f(max)), VIP2, VIP3, IIP3, IMD3 and 1 dB compression point are performed for various barrier thickness ranging from 1 nm to 4 nm. From the simulation results it is observed that performance of nanoscale DG heterostructure MOSFET is affected by the variation of barrier thickness of the device. (C) 2015 Elsevier Ltd. All rights reserved.
引用
收藏
页码：95 / 104
页数：10
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