Formal verification and hardware design with statecharts

被引：0

作者：

Philipps, J ^{[1
]}

Scholz, P ^{[1
]}

机构：

[1] Tech Univ Munich, Inst Informat, D-80290 Munich, Germany

来源：

PROSPECTS FOR HARDWARE FOUNDATIONS: ESPRIT WORKING GROUP 8533 NADA - NEW HARDWARE DESIGN METHODS SURVEY CHAPTERS | 1998年 / 1546卷

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Statecharts extend the concept of Mealy Machines by parallel composition, hierarchy, and broadcast communication. While Statecharts in principle are widely accepted in industry, some semantical concepts, especially broadcasting, are still contested. In this contribution, we present a Statechart dialect that includes the basic concepts of the language and present a formal, relational semantics for it. We show that this semantics can be used for both formal verification by model checking and hardware synthesis.

引用

页码：356 / 389

页数：34

共 50 条

[1] Formal Verification of UML Statecharts using the LOTOS Formal Language
Javani, Mohamad
Neysiani, Behzad Soleimani
Babamir, Seyed Morteza
2015 2ND INTERNATIONAL CONFERENCE ON KNOWLEDGE-BASED ENGINEERING AND INNOVATION (KBEI), 2015, : 754 - 760
[2] Formal verification of Statecharts with instantaneous chain reactions
Philipps, J
Scholz, P
TOOLS AND ALGORITHMS FOR THE CONSTRUCTION AND ANALYSIS OF SYSTEMS, 1997, 1217 : 224 - 238
[3] Optimized arithmetic hardware design based on hierarchical formal verification
Kikkeri, Nikhil
Seidel, Peter-Michael
2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, : 541 - 544
[4] Accessible formal verification for safety-critical hardware design
Lach, John
Bingham, Scott
Elks, Carl
Lenhart, Travis
Nguyen, Thuy
Salaun, Patrick
2006 PROCEEDINGS - ANNUAL RELIABILITY AND MAINTAINABILITY SYMPOSIUM, VOLS 1 AND 2, 2006, : 29 - +
[5] Formal verification of UML statecharts with real-time extensions
David, A
Möller, MO
Yi, W
FUNDAMENTAL APPROACHES TO SOFTWARE ENGINEERING, PROCEEDINGS, 2002, 2306 : 218 - 232
[6] Formal Verification of a FIFO Component in Design of Network Monitoring Hardware
Kratochvila, Tomas
Rehak, Vojtech
Safranek, David
CESNET CONFERENCE 2006: FIRST CESNET CONFERENCE ON ADVANCED COMMUNICATIONS AND GRIDS, 2006, : 151 - 160
[7] On formal equivalence verification of hardware
Khasidashvili, Zurab
COMPUTER SCIENCE - THEORY AND APPLICATIONS, 2008, 5010 : 11 - 12
[8] Formal verification of statecharts using finite-state model checkers
Zhao, Qianchuan
Krogh, Bruce H.
IEEE TRANSACTIONS ON CONTROL SYSTEMS TECHNOLOGY, 2006, 14 (05) : 943 - 950
[9] Formal verification of Statecharts using finite-state model checkers
Zhao, QC
Krogh, BH
PROCEEDINGS OF THE 2001 AMERICAN CONTROL CONFERENCE, VOLS 1-6, 2001, : 313 - 318
[10] Formal verification of a ubiquitous hardware component
Lu, Y
EMBEDDED SOFTWARE AND SYSTEMS, 2005, 3605 : 536 - 541

← 1 2 3 4 5 →