Design of testable multipliers for fixed-width data paths

被引:3
作者
Mukherjee, N
Rajski, J
Tyszer, J
机构
[1] MENTOR GRAPH CORP,WILSONVILLE,OR 97070
[2] POZNAN TECH UNIV,INST ELECT & TELECOMMUN,PL-60965 POZNAN,POLAND
基金
加拿大自然科学与工程研究理事会;
关键词
behavioral synthesis; built-in self test; design for testability; fixed-width data-dominated circuits; state coverage; residue number system arithmetic;
D O I
10.1109/12.599900
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The usage of multipliers in fixed-width data-dominated architectures (also termed data paths) poses serious testability problems. Due to truncation of their outputs, the fault observability of the multipliers degrades,and the resulting output patterns are inadequate to completely test functional blocks that are driven by them. Consequently, the overall random pattern testability of data paths deteriorates substantially. In this paper, we propose new generic design schemes, based on residue number system arithmetic, to improve the overall testability of data paths. The approach uses, in the test mode, the truncated least significant bits of the product to increase the variety of patterns at the output of a multiplier. This, in turn, improves the fault detectability of multipliers, and consequently, have a remarkable impact on the overall testability of data paths. The proposed techniques can be incorporated with a minimal performance degradation and area overhead, and are independent of the multiplier architecture. Experimental analysis performed on four high-revel synthesis benchmarks exhibits a significant improvement in the overall testability of the corresponding data-path implementations.
引用
收藏
页码:795 / 810
页数:16
相关论文
共 20 条
[1]  
ADHAM SA, 1995, P CICC
[2]  
AVRA L, 1992, P INT TEST C, P272
[3]  
Chickermane V., 1992, Proceedings International Test Conference 1992 (Cat. No.92CH3191-4), P752, DOI 10.1109/TEST.1992.527897
[4]  
CHIU S, 1991, P DES AUT C JUN, P271
[5]  
Dey S., 1994, Proceedings 12th IEEE VLSI Test Symposium (Cat. No.94TH0645-2), P2, DOI 10.1109/VTEST.1994.292342
[6]   DATA-DRIVEN MULTICOMPUTERS IN DIGITAL SIGNAL-PROCESSING [J].
GAUDIOT, JL .
PROCEEDINGS OF THE IEEE, 1987, 75 (09) :1220-1234
[7]  
Gizopoulos D., 1994, Proceedings of the Third Asian Test Symposium (Cat. No.94TH8016), P163, DOI 10.1109/ATS.1994.367236
[8]  
Graham R.L., 1989, Concrete Mathematics
[9]  
JENKINS WK, 1993, HDB DIGITAL SIGNAL P
[10]  
KRISHNAMOORTHY G, 1992, 29TH ACM/IEEE DESIGN AUTOMATION CONFERENCE : PROCEEDINGS, P279