共 45 条
- [31] SDG vs ADG with Tied and Independent gate Options in the Subthreshold Logic for Ultra Low Power Applications 2009 2ND INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY, 2009, : 176 - 179
- [34] Sub-45nm Fully-Depleted SOI CMOS Subthreshold Logic for Ultra-Low-Power Applications 2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2008, : 57 - 58
- [36] New Steep-Slope Device of Comprehensive Properties Enhancement with Hybrid Operation Mechanism for Ultra-Low-Power Applications 2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2017,