Super Steep Subthreshold Slope PN-Body Tied SOI FET for Ultra Low Power IoT Edge Applications

被引：0

作者：

Ida, Jiro ^{[1
]}

Mori, Takayuki ^{[1
]}

机构：

[1] Kanazawa Inst Technol, Div Elect Engn, 7-1 Ohgigaoka, Nonoichi, Ishikawa 9218501, Japan

来源：

PROCEEDINGS OF 2017 7TH INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS, DESIGN, AND VERIFICATION (ICDV) | 2017年

关键词：

Steep Subthreshold Slope; SOI MOSFET; Floating Body Effect;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have proposed a super steep Subthreshold Slope (SS) "PN-Body Tied SOI-FET". It shows the super steep SS (similar to 35 mu V/dec) over 3 to 5 decades of the drain current with an ultra-low drain voltage down to 0.1V. We have also improved it to reduce the operating body voltage below 1V and have clarified that the floating body effect of the SOI is a key mechanism for appearance of a super steep SS. The research status on the device was reviewed, here.

引用

页码：56 / 57

页数：2

共 45 条

[21] Confirmation of SS=35μV/dec over 3 Decades of Drain Current and Hole Accumulation Effect on PN-Body Tied SOI Super Steep SS FET's
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[22] Analysis of Super-Steep Subthreshold Slope Body-Tied SOI MOSFET and its Possibility for Ultralow Voltage Application
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[23] Precise Transient Mechanism of Steep Subthreshold Slope PN-Body-Tied SOI-FET and Proposal of a New Structure for Reducing Leakage Current upon Turn-off
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2019 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2019), 2019, : 291 - 294
[24] 14nm Ferroelectric FinFET Technology with Steep Subthreshold Slope for Ultra Low Power Applications
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[25] Analysis of Drain Current Enhancement in "PN-Body Tied SOI-FET" -Bulk vs Surface Conduction Mode and Low Vds Saturation Effect-
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[26] Neuron Function with Single Device by using "PN-Body Tied SOI-FET" -Mimicking Leaky Integrate and Fire Characteristics-
Sasaki, Toru
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6TH IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2022), 2022, : 291 - 293
[27] Effect of Vsub and Positive Charge in Buried Oxide on Super Steep SS "PN Body-Tied SOI-FET" and Proposal of CMOS without Vsub Bias
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[28] A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect Transistors in Ultra-Low Power Analog Design
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[29] Optimizing MOS-gated thyristor using voltage-based equivalent circuit model for designing steep-subthreshold-slope PN-body-tied silicon-on-insulator FET
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JAPANESE JOURNAL OF APPLIED PHYSICS, 2018, 57 (04)
[30] High-Performance Ultra-Low Power Junctionless Nanowire FET on SOI Substrate in Subthreshold Logic Application
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2010 IEEE INTERNATIONAL SOI CONFERENCE, 2010,

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