A 15MHz BW Continuous-Time ΔΣ Modulator with High Speed Digital ELD Compensation

被引：0

作者：

Hu, Hang ^{[1
]}

Li, Manxin ^{[1
]}

Dai, Zhiyuan ^{[1
]}

Ye, Fan ^{[1
]}

Ren, Junyan ^{[1
]}

机构：

[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China

来源：

2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | 2017年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

delta-sigma (Delta Sigma) modulator in TSMC 65mn CMOS technology is presented. The digital excess loop delay (DELD) compensation for half a clock cycle which can be operated quite fast. Instead of using compensation in analog domain, the compensation is performed by means of using a high speed digital subtraction block which will result in low power dissipation. The modulator achieves 78.5dB SNDR and a 15 MHz bandwidth (BW) under 600MHz clock frequency. The power consumption equals 7.81mW drawn from a 1.2V supply voltage, which yields a state-of-the-art Walden figure of merit FOM of 39 fJ/conv-step.

引用

页码：686 / 689

页数：4