An FPGA-based infant monitoring system

被引：4

作者：

Dickinson, P ^{[1
]}

Appiah, K ^{[1
]}

Hunter, A ^{[1
]}

Ormston, S ^{[1
]}

机构：

[1] Lincoln Univ, Dept Comp & Informat, Lincoln LN6 7TS, England

来源：

FPT 05: 2005 IEEE INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY, PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/FPT.2005.1568578

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We have designed an automated visual surveillance system for monitoring sleeping infants. The low-level image processing is implemented on an embedded Xilinx's Virtex II XC2v6OOO FPGA and quantifies the level of scene activity using a specially designed background subtraction algorithm. We present our algorithm and show how we have optimised it for this platform.

引用

页码：315 / 316

页数：2

共 5 条

[1]

CROWE F, 2004, P IEE IR SIGN SYST C, P118

[2]

Datta A, 2002, INT C PATT RECOG, P433, DOI 10.1109/ICPR.2002.1044748

[3]

JOHNSTON K, 2004, P 11 EL NZ C, P118

[4] Activity summarisation and fall detection in a supportive home environment [J].

Nait-Charif, H ;

McKenna, SJ .

PROCEEDINGS OF THE 17TH INTERNATIONAL CONFERENCE ON PATTERN RECOGNITION, VOL 4, 2004, :323-326

[5]

Stauffer C., 1999, Proceedings. 1999 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (Cat. No PR00149), P246, DOI 10.1109/CVPR.1999.784637

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