Optimum Circuits for Bit-Dimension Permutations

被引：23

作者：

Garrido, Mario ^{[1
]}

Grajal, Jesus ^{[2
]}

Gustafsson, Oscar ^{[1
]}

机构：

[1] Linkoping Univ, Dept Elect Engn, S-58183 Linkoping, Sweden

[2] Univ Politecn Madrid, Dept Signal Syst & Radiocommun, E-28040 Madrid, Spain

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2019年 / 27卷 / 05期

关键词：

Bit-dimension permutation; bit reversal; data management; fast Fourier transform (FFT); matrix transposition; pipelined architecture; streaming data; Viterbi decoder; FFT; ARCHITECTURE; NETWORKS; ALGORITHMS; PROCESSOR; DESIGN;

D O I：

10.1109/TVLSI.2019.2892322

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we present a systematic approach to design hardware circuits for bit-dimension permutations. The proposed approach is based on decomposing any bit-dimension permutation into elementary bit-exchanges. Such decomposition is proven to achieve the theoretical minimum number of delays required for the permutation. This offers optimum solutions for multiple well-known problems in the literature that make use of bit-dimension permutations. This includes the design of permutation circuits for the fast Fourier transform, bit reversal, matrix transposition, stride permutations, and Viterbi decoders.

引用

页码：1148 / 1160

页数：13

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