Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

被引:79
作者
Herrera-Alzu, I. [1 ]
Lopez-Vallejo, M. [1 ]
机构
[1] Univ Politecn Madrid, Dept Elect Engn, ETSI Telecomunicac, E-28040 Madrid, Spain
关键词
Field Programmable Gate Array (FPGA); reconfiguration; scrubbing; single event upset; Xilinx; SINGLE-EVENT; MITIGATION;
D O I
10.1109/TNS.2012.2231881
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications. One drawback of this technology is that it is susceptible to ionizing radiation, and this sensitivity increases with technology scaling. This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications. Several techniques exist for coping with radiation effects at user application. In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation. Depending on the radiation environment and on the system dependability requirements, the configuration scrubber design can become more or less complex. This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers.
引用
收藏
页码:376 / 385
页数:10
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