A compact approach to on-chip interconnect heat conduction modeling using the finite element method

Over upcoming electronics technology nodes, shrinking feature sizes of on-chip interconnects and correspondingly higher current densities are expected to result in higher temperatures due to self-heating. This study describes a finite element based compact thermal modeling approach to investigate the effects of Joule heating on complex interconnect structures. In this method, interconnect cross section is assumed to be isothermal and conduction along the interconnect is retained. A composite finite element containing both metal and dielectric regions is used to discretize the interconnect stack. The compact approach predicts the maximum temperature rise in the metal to within 5-10% of the detailed numerical computations, while requiring only a fraction of elements. Computational time for the compact model solution is several seconds, versus many hours for the detailed solutions obtained through successive mesh refinement until grid independence is achieved. For a comparable number of elements, the compact model is in general much more accurate than the traditional finite element approach. To validate the simulations, temperature rise in a 500-link two-layer interconnect with a via layer was measured at several current densities. The compact method predicts the temperature rise of the 500-link chain to within 5% of the measurements thereby validating the method. The approach described here could be an efficient technique for full chip Joule heating simulations and for clock signal propagation simulations, which are performed as part of designing next generation chip architectures.