High-K gate dielectrics for sub-100 nm CMOS technology

In this paper, tile materials and processing challenges for the fabrication of high-quality. ultra-thin (EOT<1 nm) high-K gate stack for sub-100 nm CMOS technology will be reviewed along with our recent results oil CVD HfO2. The requirement for ultra thin arid robust interface layers to avoid any thickness increase due to post-deposition processing to achieve thinnest EOT will be discussed. Results will be presented on thermal stability of high-K materials, arid interfacial reactions of high-K/Si and high-K/gate electrode. We will also discuss key factors that govern the conduction and degradation mechanisms in high-K gate stack. Both poly-Si arid metal nitrides are explored as possible gate electrode materials arid tile upper thermal budget limit for such materials are discussed.