Optimization of VLSI Architectures for DTW

被引：0

作者：

Hussain, Shah Muhammed Abid ^{[1
]}

Rashid, A. B. M. Harun-ur ^{[1
]}

机构：

[1] Bangladesh Univ Engn & Technol, Dept Elect & Elect Engn, Dhaka 1000, Bangladesh

来源：

2012 7TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (ICECE) | 2012年

关键词：

VLSI; accelerator architectures; DTW; FPGA; hardware implementation; SPEECH RECOGNITION;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In data mining and time series recognition applications Dynamic Time Warping (DTW) is a very popular method. It can produce accurate results provided its originality is preserved. But its lethargic nature has been inspiring development of its hardware based acceleration methods. In this paper, four novel VLSI architectures for performing DTW are proposed and compared. The comparison reflects achievement of significant conclusions specifically for performance critical and memory constraint applications.

引用

页数：4

共 6 条

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