A 6GS/s, 4-bit receiver analog-to-digital converter with embedded DFE

被引：0

作者：

Varzaghani, A ^{[1
]}

Yang, CKK ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Los Angeles, CA 90095 USA

来源：

2005 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2005年

关键词：

analog-to-digital converter; decision-feedback-equalizer; code-overlapping; signal-to-noise ratio; pipeline; resolution and CMOS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 4-bit 6GS/s A/D converter is designed for a serial-link receiver and features an embedded adjustable one-tap DFE. Feedback-delay is relaxed through applying DFE to a 10-way interleaved pipelined architecture. Code-overlapping is used to remove residual ISI. Measured performance at 6GS/s shows 22.5dB of low-frequency input SNDR. DFE tap-coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. The 1.8x1.6mm(2) chip is fabricated in 0.18 mu m CMOS technology and consumes 780mW at 1.8V power-supply.

引用

页码：322 / 325

页数：4

共 8 条

[1] A 2Gb/s 2-tap DFE receiver for mult-drop single-ended signaling systems with reduced noise
Bae, SJ
Chi, HJ
Sohn, YS
Park, HJ
[J]. 2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 : 244 - 245
[2] Ginetti B, 1988, VLSI S CIRC, P125
[3] Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL
Maneatis, JG
Kim, J
McClatchie, L
Maxey, J
Shankaradas, M
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (11) : 1795 - 1803
[4] Poulton K, 2003, ISSCC DIG TECH PAP I, V46, P318
[5] Razavi B., 2002, DESIGN ANALOG CMOS I
[6] Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver
Stojanovic, V
Ho, A
Garlepp, B
Chen, F
Wei, J
Alon, E
Werner, C
Zerbe, J
Horowitz, MA
[J]. 2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, : 348 - 351
[7] A 600MS/s, 5-bit pipelined analog-to-digital converter for serial-link applications
Varzaghani, A
Yang, CKK
[J]. 2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, : 276 - 279
[8] A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS
Yang, CKK
Stojanovic, V
Modjtahedi, S
Horowitz, MA
Ellersick, WF
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (11) : 1684 - 1692

← 1 →