A 6GS/s, 4-bit receiver analog-to-digital converter with embedded DFE

被引：0

作者：

Varzaghani, A ^{[1
]}

Yang, CKK ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Los Angeles, CA 90095 USA

来源：

2005 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2005年

关键词：

analog-to-digital converter; decision-feedback-equalizer; code-overlapping; signal-to-noise ratio; pipeline; resolution and CMOS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 4-bit 6GS/s A/D converter is designed for a serial-link receiver and features an embedded adjustable one-tap DFE. Feedback-delay is relaxed through applying DFE to a 10-way interleaved pipelined architecture. Code-overlapping is used to remove residual ISI. Measured performance at 6GS/s shows 22.5dB of low-frequency input SNDR. DFE tap-coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. The 1.8x1.6mm(2) chip is fabricated in 0.18 mu m CMOS technology and consumes 780mW at 1.8V power-supply.

引用

页码：322 / 325

页数：4

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