High Speed. Pipelined 64-Point FFT Processor based on Radix-22 for Wireless LAN

被引：0

作者：

Bansal, Manish ^{[1
]}

Nakhate, Sangeeta ^{[1
]}

机构：

[1] MANIT, Dept EC Engn, Bhopal, India

来源：

2017 4TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN) | 2017年

关键词：

FFT; CFA; Radix-2(2); complex multiplier; SDF; WLAN;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This Paper presents high Speed pipeline 64-point EFL processor based on Radix-21 for wireless LAIN communication systems. This method uses Radix-2 butterfly structure and Radix-21 CFA algorithm. Radix-2 butterfly's complexity is very low and Radix-22 CIA algorithm reduces number of twiddle factors compared to Radix-4 and Radix-2. An efficient HIDE code has been written, synthesized successfully using XST of Xilinx ISE 14.1 and simulated using ModeiSim PE Student Edition 10.4a. Also MATLAB code has been written and simulated with MATLAB R2012a tool. The computation speed of proposed design is observed to be 15896 MHz after the synthesis process and SQNR 37.02dB for 64 point.

引用

页码：607 / 612

页数：6

共 18 条

[1]

Akshata U, 2013, MIT INT J ELECT COMM, P39

[2]

[Anonymous], INT J ENG TECHNOLOGY

[3]

[Anonymous], 2000, DIGIT SIGNAL PROCESS

[4] An OMM-specified lossless FFT architecture [J].

Chang, Wei-Hsin ;

Nguyen, Truong .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2006, 53 (06) :1235-1243

[5]

Chang Wei-Hsin, 2013, INT J ENG TRENDS TEC, P109

[6]

Cho T, 2011, IEEE INT SYMP CIRC S, P1259

[7]

Cho Taesang, 2013, IEEE T VERY LARGE SC, P187

[8] Digital OFDM Transmitter Architecture and FPGA Design [J].

Cui, Xiaoxin ;

Yu, Dunshan .

2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, :477-480

[9]

Fan Chih-Peng, 2008, J ENG, V19, P61

[10]

Garrido Mario, 2013, ISME J, P1

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