A 4 x 14-Gbps/ch VCSEL array driving ASIC in 65 nm CMOS for high-energy physics experiments

被引：2

作者：

Guo, D. ^{[1
]}

Sun, Q. ^{[2
]}

Gong, D. ^{[2
]}

Hou, S. ^{[3
]}

Liu, C. ^{[2
]}

Lin, H. ^{[1
]}

Liu, T. ^{[2
]}

Xiao, L. ^{[1
]}

Yang, D. ^{[4
]}

Ye, J. ^{[2
]}

Zhou, W. ^{[1
]}

机构：

[1] Cent China Normal Univ, Dept Phys, Wuhan 430079, Hubei, Peoples R China

[2] Southern Methodist Univ, Dept Phys, Dallas, TX 75275 USA

[3] Acad Sinica, Inst Phys, Taipei 11529, Taiwan

[4] Univ Sci & Technol China, State Key Lab Particle Detect & Elect, Hefei 230026, Anhui, Peoples R China

来源：

JOURNAL OF INSTRUMENTATION | 2019年 / 14卷

基金：

中国国家自然科学基金;

关键词：

Front-end electronics for detector readout; Optical detector readout concepts; Analogue electronic circuits; Radiation-hard electronics; TRANSMITTER;

D O I：

10.1088/1748-0221/14/05/C05016

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

This paper presents the design and test results of a 4 x 14 Gb/s vertical cavity surface emitting laser (VCSEL) array driver VLAD14 fabricated in 65 nm CMOS technology. A novel output driving stage in VLAD14 is proposed to improve the bandwidth comparing to the conventional structure. VLAD14 outputs a 2mA bias current and a 6mA modulation current with a power consumption of 52 mW/ch when working at 14 Gbps/ch. The driver die has been tested with the VCSEL array load and wide-open optical eyes have been captured at 14 Gbps/ch.

引用

页数：8

共 2 条

[1] Developments of two 4 x 10 Gb/s VCSEL array drivers in 65 nm CMOS for HEP experiments
Guo, D.
Gong, D.
Xiang, A. C.
Moreira, P.
Kulis, S.
Chen, J.
Hou, S.
Liu, C.
Liu, T.
Prosser, A.
He, H.
Sun, Q.
Wang, J.
Yang, D.
Ye, J.
Zhou, W.
JOURNAL OF INSTRUMENTATION, 2017, 12
[2] QTIA, a 2.5 or 10 Gbps 4-channel array optical receiver ASIC in a 65 nm CMOS technology
Sun, H.
Huang, X.
Chao, C. -P.
Chen, S. -W.
Deng, B.
Gong, D.
Hou, S.
Huang, G.
Kulis, S.
Li, C. -Y.
Liu, C.
Liu, T.
Moreira, P.
Sun, Q.
Ye, J.
Zhang, L.
Zhang, W.
JOURNAL OF INSTRUMENTATION, 2022, 17 (05):

← 1 →