Wafer fabrication ion implant charging - Impact on gate oxide breakdown
被引:0
作者:
Yeoh, TS
论文数: 0引用数: 0
h-index: 0
机构:
Intel Technol Sdn Bhd, Penang 11900, MalaysiaIntel Technol Sdn Bhd, Penang 11900, Malaysia
Yeoh, TS
[1
]
Hu, SJ
论文数: 0引用数: 0
h-index: 0
机构:
Intel Technol Sdn Bhd, Penang 11900, MalaysiaIntel Technol Sdn Bhd, Penang 11900, Malaysia
Hu, SJ
[1
]
机构:
[1] Intel Technol Sdn Bhd, Penang 11900, Malaysia
来源:
ICSE'98: 1998 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS
|
1998年
关键词:
D O I:
10.1109/SMELEC.1998.781153
中图分类号:
TM [电工技术];
TN [电子技术、通信技术];
学科分类号:
0808 ;
0809 ;
摘要:
Process induced charging is not new in the wafer fabrication process. However, it is difficult to identify as test structures used cannot detect this problem effectively as these structures are not connected to large metal or polysilicon network for charge collection or if these structures are covered by thick photoresist. Ion implantation is a major process where charging poses a problem to the extent of transistor gate oxide breakdown or degradation. This will be presented along with their respective charging models. This breakdown is strongly influenced by device design layout, implanter energy and diffusion breakdown strengths.