A high-performance VLSI architecture for advanced encryption standard (AES) algorithm

被引：0
|
作者：
Kosaraju, NM [1 ]
Varanasi, M [1 ]
Mohanty, SP [1 ]
机构：
[1] Univ S Florida, Tampa, FL 33613 USA
来源：
19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The subkeys, required for each round of the Rijndael algorithm, are generated in real-time by the key-scheduler module by expanding the initial secret key, thus reducing the amount of storage for buffering. Moreover, pipelining is used after each standard round to enhance the throughput. A prototype chip implemented using 0.35 mu CMOS technology resulted in a throughput of 232Mbps for iterative architecture and 1.83Gbps for pipelining architecture.
引用
收藏
页码：481 / 484
页数：4
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