A high-performance VLSI architecture for advanced encryption standard (AES) algorithm

被引：0
|
作者：
Kosaraju, NM [1 ]
Varanasi, M [1 ]
Mohanty, SP [1 ]
机构：
[1] Univ S Florida, Tampa, FL 33613 USA
来源：
19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The subkeys, required for each round of the Rijndael algorithm, are generated in real-time by the key-scheduler module by expanding the initial secret key, thus reducing the amount of storage for buffering. Moreover, pipelining is used after each standard round to enhance the throughput. A prototype chip implemented using 0.35 mu CMOS technology resulted in a throughput of 232Mbps for iterative architecture and 1.83Gbps for pipelining architecture.
引用
收藏
页码：481 / 484
页数：4
相关论文
共 50 条
  • [1] An Advanced Encryption Standard in Memory (AESIM) Efficient, High Performance S-box Based AES Encryption and Decryption Architecture on VLSI
    Padmavathi, R. Anusha
    Dhanalakshmi, K. S.
    WIRELESS PERSONAL COMMUNICATIONS, 2022, 123 (04) : 3081 - 3101
  • [2] An Advanced Encryption Standard in Memory (AESIM) Efficient, High Performance S-box Based AES Encryption and Decryption Architecture on VLSI
    R. Anusha Padmavathi
    K. S. Dhanalakshmi
    Wireless Personal Communications, 2022, 123 : 3081 - 3101
  • [3] High Throughput Architecture for the Advanced Encryption Standard Algorithm
    Hesham, Salma
    Abd El Ghany, Mohamed A.
    Hofmann, Klaus
    PROCEEDINGS OF THE 2014 IEEE 17TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2014, : 167 - 170
  • [4] Performance evaluation of hardware models of advanced encryption standard (AES) algorithm
    Yenuguvanilanka, Jyothi
    Elkeelany, Omar
    PROCEEDINGS IEEE SOUTHEASTCON 2008, VOLS 1 AND 2, 2008, : 222 - 225
  • [5] High-performance VLSI architecture for the Viterbi algorithm
    Boo, M
    Arguello, F
    Bruguera, JD
    Doallo, R
    Zapata, EL
    IEEE TRANSACTIONS ON COMMUNICATIONS, 1997, 45 (02) : 168 - 176
  • [6] Performance Analysis of Advanced Encryption Standard (AES)
    Xiao, Yang
    Sun, Bo
    Chen, Hsiao-Hwa
    GLOBECOM 2006 - 2006 IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE, 2006,
  • [7] High-Speed architecture for Advanced Encryption Standard Algorithm
    Rachh, Rashmi Ramesh
    AnandaMohan, P. V.
    Anami, B. S.
    2012 ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN MICROELECTRONICS & ELECTRONICS (PRIMEASIA), 2012, : 167 - 172
  • [8] Digital Image Encryption Based On Advanced Encryption Standard(AES) Algorithm
    Zhang, Qi
    Qun, Ding
    2015 FIFTH INTERNATIONAL CONFERENCE ON INSTRUMENTATION AND MEASUREMENT, COMPUTER, COMMUNICATION AND CONTROL (IMCCC), 2015, : 1218 - 1221
  • [9] Low-cost Advanced Encryption Standard (AES) VLSI architecture: A minimalist bit-serial approach
    Hernandez, OJ
    Sodon, T
    Adel, M
    PROCEEDINGS OF THE IEEE SOUTHEASTCON 2004: EXCELLENCE IN ENGINEERING, SCIENCE, AND TECHNOLOGY, 2005, : 121 - 125
  • [10] Advanced Encryption Standard (AES)
    Network Box
    Netw. Secur., 2009, 12 (8-12):
12345