First Demonstration of Junctionless Accumulation-Mode Bulk FinFETs With Robust Junction Isolation

被引：62

作者：

Kim, Tae Kyun ^{[1
]}

Kim, Dong Hyun ^{[1
]}

Yoon, Young Gwang ^{[1
]}

Moon, Jung Min ^{[1
]}

Hwang, Byeong Woon ^{[1
]}

Moon, Dong-Il ^{[1
]}

Lee, Gi Seong ^{[2
]}

Lee, Dong Wook ^{[2
]}

Yoo, Dong Eun ^{[2
]}

Hwang, Hae Chul ^{[2
]}

Kim, Jin Soo ^{[2
]}

Choi, Yang-Kyu ^{[1
]}

Cho, Byung Jin ^{[1
]}

Lee, Seok-Hee ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept Elect Engn, Taejon 305701, South Korea

[2] Natl Nanofab Ctr, Taejon 305701, South Korea

来源：

IEEE ELECTRON DEVICE LETTERS | 2013年 / 34卷 / 12期

关键词：

Junction isolation; junctionless (JL) field-effect transistor (FET); junctionless-accumulation-mode (JAM) FET; Si bulk FinFET; PERFORMANCE; TRANSISTORS; DEVICE; DESIGN;

D O I：

10.1109/LED.2013.2283291

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A junctionless-accumulation-mode (JAM) p-channel MOSFET is successfully implemented based on a junction-isolated bulk FinFET for the first time. The JAM devices with a fin width of 16 nm show outstanding transfer characteristics: 1) subthreshold swing (SSmin) = 68 mV/dec; 2) drain-induced-barrier-lowering is 9 mV/V; and 3) I-ON/I-OFF ratio > 1x10(6). The JAM devices with smaller fin widths or longer gate lengths give superior short-channel characteristics and higher threshold voltages (V-th) due to their enhanced gate electrostatic controllability. The reverse back bias modulates V-th and SS favorably by virtue of a body-tied device, maintaining the substrate current due to junction leakage of <1x10(-11) A.

引用

页码：1479 / 1481

页数：3

共 16 条

[1]

[Anonymous], 2009, ENV ECOLOG P

[2] Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm [J].

Barraud, S. ;

Berthome, M. ;

Coquand, R. ;

Casse, M. ;

Ernst, T. ;

Samson, M. -P. ;

Perreau, P. ;

Bourdelle, K. K. ;

Faynot, O. ;

Poiroux, T. .

IEEE ELECTRON DEVICE LETTERS, 2012, 33 (09) :1225-1227

[3] Junctionless Nanowire Transistor (JNT): Properties and design guidelines [J].

Colinge, J. P. ;

Kranti, A. ;

Yan, R. ;

Lee, C. W. ;

Ferain, I. ;

Yu, R. ;

Akhavan, N. Dehdashti ;

Razavi, P. .

SOLID-STATE ELECTRONICS, 2011, 65-66 :33-37

[4]

Colinge JP, 2010, NAT NANOTECHNOL, V5, P225, DOI [10.1038/nnano.2010.15, 10.1038/NNANO.2010.15]

[5] Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling [J].

Gundapaneni, Suresh ;

Ganguly, Swaroop ;

Kottantharayil, Anil .

IEEE ELECTRON DEVICE LETTERS, 2011, 32 (03) :261-263

[6] Device and Circuit Performance Estimation of Junctionless Bulk FinFETs [J].

Han, Ming-Hung ;

Chang, Chun-Yen ;

Chen, Hung-Bin ;

Cheng, Ya-Chi ;

Wu, Yung-Chun .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (06) :1807-1813

[7] Performance Comparison Between Bulk and SOI Junctionless Transistors [J].

Han, Ming-Hung ;

Chang, Chun-Yen ;

Chen, Hung-Bin ;

Wu, Jia-Jiun ;

Cheng, Ya-Chi ;

Wu, Yung-Chun .

IEEE ELECTRON DEVICE LETTERS, 2013, 34 (02) :169-171

[8] Low-temperature electrical characterization of junctionless transistors [J].

Jeon, Dae-Young ;

Park, So Jeong ;

Mouis, Mireille ;

Barraud, Sylvain ;

Kim, Gyu-Tae ;

Ghibaudo, Gerard .

SOLID-STATE ELECTRONICS, 2013, 80 :135-141

[9]

Kranti A., 2010, ESSDERC 2010 - 40th European Solid State Device Research Conference, P357, DOI 10.1109/ESSDERC.2010.5618216

[10] Performance estimation of junctionless multigate transistors [J].

Lee, Chi-Woo ;

Ferain, Isabelle ;

Afzalian, Aryan ;

Yan, Ran ;

Akhavan, Nima Delidashti ;

Razavi, Pedrarn ;

Colinge, Jean-Pierre .

SOLID-STATE ELECTRONICS, 2010, 54 (02) :97-103

← 1 2 →