A 1.2V 250mW 14b 100MS/s digitally calibrated pipeline ADC in 90nm CMOS

被引：0

作者：

de Vel, Hans Van ^{[1
]}

Buter, Berry ^{[1
]}

van der Ploeg, Hendrik ^{[1
]}

Vertregt, Maarten ^{[1
]}

Geelen, Govert ^{[1
]}

Paulus, Edward ^{[1
]}

机构：

[1] NXP Semicond, Eindhoven, Netherlands

来源：

2008 IEEE SYMPOSIUM ON VLSI CIRCUITS | 2008年

关键词：

A/D conversion; pipeline ADC; digital calibration; deep-submicron CMOS and low supply voltage;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 14b pipeline ADC is realized in 90nm CMOS at a 1.2V supply. Enabling techniques are range-scaling in the first pipeline stage with charge-reset and digital background calibration of non-linearity. The ADC achieves 73dB SNR and 91dB SFDR at 100MS/s sampling rate and 250mW power consumption. The 73dB SNDR performance is maintained within 3dB up to a Nyquist input frequency and the FOM is 0.7pJ/conv.

引用

页码：59 / 60

页数：2