Implementing a Performance Improved Controller for SoC

被引：0

作者：

Harathi, Vellampati ^{[1
]}

Raju, Govinda M. ^{[2
]}

Praveen, S. ^{[2
]}

机构：

[1] RV Coll Engn, VLSI & Embedded Syst, Bangalore, Karnataka, India

[2] RV Coll Engn, Dept ECE, Bangalore, Karnataka, India

来源：

PROCEEDINGS OF 2017 INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING AND CONTROL (I2C2) | 2017年

关键词：

Time to market; Low cost; G5; SoC; Controller; Patch creation;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

With increasing complexities of semiconductor devices due to growing performance, functionality requirements and with diminished time to market, the semiconductor firms try to develop null defect products in very less development time [1]. In SoC, controller plays a vital role and it is responsible for data transfers between blocks of the system, initialization and configuration, programming, power management, etc. The processor present in the controller executes the firmware from non-volatile memory (ROM). Replacement of the firmware might be required if there are defects in the pre-loaded code or if the additional feature is needs to be implemented. But, replacing the firmware is very tedious and time consuming task and also it requires additional fabrication steps which could prove costly. Due this reason, incorrect functions present in the firmware can be corrected with the expected functionality in Private Non Volatile Memory (PNVM) as a separate patch. This paper presents design & simulation of the PNVM patch for fifth generation SoC (G5) based on Cortex M3 core.

引用

页数：6