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- [42] Design of a Two-Step Low-Power and High-Speed CMOS Flash ADC Architecture 2020 24TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST (VDAT), 2020,
- [43] Ultra Low-Power High-Speed Single-Bit Hybrid Full Adder Circuit 2017 8TH INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES (ICCCNT), 2017,
- [44] Low Power High Speed Full Adder Cell with XOR/XNOR Logic Gates in 90nmTechnology 2017 INTERNATIONAL CONFERENCE ON TECHNICAL ADVANCEMENTS IN COMPUTERS AND COMMUNICATIONS (ICTACC), 2017, : 61 - 65
- [46] High Speed Low Power 64-Bit Comparator Designed Using Current Comparison Based Domino Logic 2015 2ND INTERNATIONAL CONFERENCE ON ELECTRONICS AND COMMUNICATION SYSTEMS (ICECS), 2015, : 155 - 161
- [47] Design of a High Speed, Low Power Synchronously Clocked NOR-based JK Flip-Flop using Modified GDI Technique in 45nm Technology 2014 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI), 2014, : 600 - 606
- [48] Reduction of Kickback Noise in a High-Speed, Low-Power Domino Logic-Based Clocked Regenerative Comparator ICCCE 2018, 2019, 500 : 439 - 447