Effect of time delay on the pull-in range of phase locked loops

The pull-in range of phase locked loop (PLL) is a key parameter for evaluating the performance of the PLL circuit. It is defined as the maximum detuning frequency range where the loop locks. Different methods have been proposed for computing the pull-in range of phase locked loops in the absence of time delay. In this paper, the effect of time delay on the pull-in range of second-order phase locked loop as well as its dynamical behavior will be discussed. The time delay is modeled using first order Pade approximation. Using Pade approximation, the nonlinear second order delay differential equation which describes the phase error dynamic of the PLL is transformed into fourth order system in the state space representation. The new time-delay PLL model is simulated and different behavior is observed which is different than a typical PLL system without delay. As the gain of the loop increases, new behavior such as change of circuit stability and chaos are recognized which suggests that the gain of the loop cannot be arbitrary large. We compare the pull-in range of a time delay PLL with those without time delay. Results demonstrate the degradation in the pull-in range for the time delay PLL. Moreover, result shows that the pull in range gets narrower as time delay increases.