DFT for delay fault testing of high-performance digital circuits

被引：7
作者：
Chatterjee, B
Sachdev, M
Keshavarzi, A
机构：
[1] Univ Waterloo, Dept Elect & Comp Engn, Waterloo, ON N21 3G1, Canada
[2] Intel Corp, Microproc Res Labs, Portland, OR USA
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2004年 / 21卷 / 03期
关键词：
D O I：
10.1109/MDT.2004.10
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Timing-only parametric defects are a major source of failures and test escapes in modern ICs. A DFT technique using compound domino logic gates with footer transistors uncovers these hard-to-detect defects with minimal performance and power overheads.
引用
收藏
页码：248 / 258
页数：11
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