Fault-Tolerant Network Interface for Spatial Division Multiplexing Based Network-on-Chip

被引：0

作者：

Das, Anup ^{[1
]}

Kumar, Akash ^{[1
]}

Veeravalli, Bharadwaj ^{[1
]}

机构：

[1] Natl Univ Singapore, Dept Elect & Comp Engn, Singapore 117548, Singapore

来源：

2012 7TH INTERNATIONAL WORKSHOP ON RECONFIGURABLE AND COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC) | 2012年

关键词：

Fault-Tolerance; Network-on-Chip; Spatial Division Multiplexing; Network Interface;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The progressive maturity of VLSI manufacturing technology is helping in integrating more and more processing elements and memory units on a single die to form a Multiprocessor System-On-Chip (MPSoC). Network-on-Chip (NoC) is adopted as communication backbone for most of these modern day multiprocessor systems. As complexity of these system scales, there has been a growing concern on the dependability of these processing and communication elements. In this paper, we propose a centralized hardware fault-tolerant network interface (NI) for NoCs based on spatial division multiplexing. Experiments show that the proposed design has better throughput than a non fault-tolerant design with only 18% area overhead. We also introduce an area optimized distributed fault- tolerant NI architecture which provides 50% more throughput than the centralized design for high fault rates.

引用

页数：8