3D Full-Wave Simulation of Stub Length Effect of Vias in High Speed PCB Design

被引：0
|
作者：
Steenbergen, Eric [1 ,2 ]
Moonen, Niek [1 ]
Leferink, Frank [1 ,3 ]
机构：
[1] Univ Twente, Enschede, Netherlands
[2] Neways Technol BV, Enschede, Netherlands
[3] THALES Nederland BV, Vengelo, Netherlands
来源：
PROCEEDINGS OF THE 2021 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC 2021) | 2021年
关键词：
Via stubs; via shielding; EMI; impedance mismatches; PRINTED-CIRCUIT BOARDS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Throughout this paper, signal integrity (SI) problems in high-speed PCB design have been addressed as being a result of via stubs and fabrication tolerances that are present throughout PCB transmission lines. Robust PCB design must be ensured as signal rise and fall times have shortened, which is modeled within the 3D EM simulation environment of CST Studio. It is shown that the insertion loss of the signal is affected by the resonance frequency of the via stub, and impedance mismatches throughout the transmission lines. Shielding techniques have been investigated to combat these effects on SI, and have shown a significant improvement in bandwidth as a result.
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页数：4
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