An Efficient Finite Field Multiplier Using Redundant Representation

被引：6
|
作者：
Namin, Ashkan Hosseinzadeh [1 ]
Wu, Huapeng [1 ]
Ahmadi, Majid [1 ]
机构：
[1] Univ Windsor, Dept Elect & Comp Engn, Windsor, ON N9B 3P4, Canada
来源：
ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS | 2012年 / 11卷 / 02期
基金：
加拿大自然科学与工程研究理事会;
关键词：
Algorithms; Security; Multiplier; finite field; redundant representation; security; IMPLEMENTATION; GF(2(M));
D O I：
10.1145/2220336.2220343
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An efficient word-level finite field multiplier using redundant representation is proposed. The proposed multiplier has a significantly higher speed, compared to previously proposed word-level architectures using either redundant representation or optimal normal basis type I, at the expense of moderately higher area complexity. Furthermore, the new design out-performs other similar proposals when considering the product of area and delay as a measure of performance. ASIC Realization of the proposed design using TSMC's .18 mu m CMOS technology for the binary field size of 163 is also presented.
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收藏
页数：14
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