Development of 3-D Silicon Module With TSV for System in Packaging

被引：80

作者：

Khan, Navas ^{[1
]}

Rao, Vempati Srinivasa ^{[1
]}

Lim, Samuel ^{[1
]}

We, Ho Soon ^{[1
]}

Lee, Vincent ^{[1
]}

Zhang, Xiaowu ^{[1
]}

Liao, E. B. ^{[1
]}

Nagarajan, Ranganathan ^{[1
]}

Chai, T. C. ^{[1
]}

Kripesh, V. ^{[1
]}

Lau, John H. ^{[1
]}

机构：

[1] Inst Microelect, Microsyst Modules & Components Lab, Singapore 117685, Singapore

来源：

IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES | 2010年 / 33卷 / 01期

关键词：

3-D packaging; system in packaging; through silicon via;

D O I：

10.1109/TCAPT.2009.2037608

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Portable electronic products demand multifunctional module comprising of digital, radio frequency and memory functions. Through silicon via (TSV) technology provides a means of implementing complex, multifunctional integration with a higher packing density for a system in package. A 3-D silicon module with TSV has been developed in this paper. Thermo-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the barrier copper via is exposed by the backgrinding process. A two-stack silicon module is developed and module fabrication details are given in this paper. The module reliability has been evaluated under temperature cycling (-40/125 degrees C) and drop test.

引用

页码：3 / 9

页数：7

共 7 条

[1] A review of 3-D packaging technology [J].

Al-Sarawi, SF ;

Abbott, D ;

Franzon, PD .

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING, 1998, 21 (01) :2-14

[2]

*HIBB KARLSS SOR I, ABAQUS 6 41

[3] Development of 3D stack package using silicon interposer for high power application [J].

Khan, Navas ;

Yoon, S. W. ;

Viswanath, Akella G. K. ;

Ganesh, V. P. ;

Ranganathan ;

Witarsa, David ;

Lim, Samuel ;

Vaidyanathan, Kripesh .

56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS, 2006, :756-+

[4] Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection [J].

Knickerbocker, JU ;

Andry, PS ;

Buchwalter, LP ;

Deutsch, A ;

Horton, RR ;

Jenkins, KA ;

Kwark, YH ;

McVicker, G ;

Patel, CS ;

Polastre, RJ ;

Schuster, C ;

Sharma, A ;

Sri-Jayantha, SM ;

Surovic, CW ;

Tsang, CK ;

Webb, BC ;

Wright, SL ;

McKnight, SR ;

Sprogis, EJ ;

Dang, B .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2005, 49 (4-5) :725-753

[5] High performance embedded RF passive device process integration [J].

Li, H. Y. ;

Khoo, Y. M. ;

Khan, Navas ;

Teoh, K. W. ;

Rao, Vempati Srinivasa ;

Li, H. B. ;

Liao, E. B. ;

Mohanraj, S. ;

Kripesh, V. ;

Rakesh, K. .

58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, :1709-1713

[6] Three-dimensional very thin stacked packaging technology for SiP [J].

Yano, Y ;

Sugiyama, T ;

Ishihara, S ;

Fukui, Y ;

Juso, H ;

Miyata, K ;

Sota, Y ;

Fujita, K .

52ND ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2002 PROCEEDINGS, 2002, :1329-1334

[7]

Yoon SW, 2006, ELEC COMP C, P1449

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