Run-Time Task Allocation Considering User Behavior in Embedded Multiprocessor Networks-on-Chip

被引：47
作者：
Chou, Chen-Ling [1 ]
Marculescu, Radu [1 ]
机构：
[1] Carnegie Mellon Univ, Dept Elect & Comp Engn, Pittsburgh, PA 15213 USA
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2010年 / 29卷 / 01期
基金：
美国国家科学基金会;
关键词：
Low-power design; multiprocessor interconnection; networks-on-chip; optimization methods; resource management; user behavior; SYSTEM;
D O I：
10.1109/TCAD.2009.2034348
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we propose a run-time strategy for allocating application tasks to embedded multiprocessor systems-on-chip platforms where communication happens via the network-on-chip approach. As a novel contribution, we incorporate the user behavior information in the resource allocation process; this allows the system to better respond to real-time changes and to adapt dynamically to different user needs. Several algorithms are proposed for solving the task allocation problem while minimizing the communication energy consumption and network contention. When the user behavior is taken into consideration, we observe more than 70% communication energy savings (with negligible energy and run-time overhead) compared to an arbitrary contiguous task allocation strategy.
引用
收藏
页码：78 / 91
页数：14
相关论文
共 33 条
[21]  
Mache J., 1996, CISTR9613 U OR
[22]   Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives [J].
Marculescu, Radu ;
Ogras, Umit Y. ;
Peh, Li-Shiuan ;
Jerger, Natalie Enright ;
Hoskote, Yatin .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2009, 28 (01) :3-21
[23]  
MOREIRA O, 2007, P 2007 ACM S APPL CO, P1557
[24]   Bandwidth-constrained mapping of cores onto NoC architectures [J].
Murali, S ;
De Micheli, G .
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, :896-901
[25]   Centralized run-time resource management in a network-on-chip containing reconfigurable hardware tiles [J].
Nollet, V ;
Marescaux, T ;
Avasare, P ;
Verkest, D ;
Mignolet, JY .
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, :234-239
[26]   Operating-system controlled network on chip [J].
Nollet, V ;
Marescaux, T ;
Verkest, D ;
Mignolet, JY ;
Vernalde, S .
41ST DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2004, 2004, :256-259
[27]  
PASTRNAK AM, 2006, P VIS COMM IM PROC S
[28]  
Pop P, 2001, DES AUT CON, P450, DOI 10.1109/DAC.2001.935551
[29]  
SMIT T. L., 2004, P 4 PROGRESS WORKSH, P185
[30]  
SRINIVASAN M, 2006, P DES AUT TEST MUN G, P1
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