A test approach for look-up table based FPGAs

被引：7

作者：

Atoofian, E ^{[1
]}

Navabi, Z ^{[1
]}

机构：

[1] Univ Tehran, Dept Elect & Comp Engn, Tehran 14399, Iran

来源：

JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY | 2006年 / 21卷 / 01期

关键词：

FPGA testing; BIST; LUT testing; memory testing; TPG with LE;

D O I：

10.1007/s11390-006-0141-6

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a test architecture for minimum number of test configurations in test of FPGA (Field Programmable Gate Array) LUTs (Look Up Tables). The test architecture includes a TPC (Test Pattern Generator) that is tested while it is generating test data for LEs (Logic Elements) that form the CUT (Circuit Under Test). This scheme eliminates the need for switching LEs between CUT, TPG and ORA (Output Response Analyzer) and having to perform many more reconfigurations of the FPGA. An external ORA locates faults of the FPGA under test. In addition to the LUTs, a scheme is presented for testing other parts of LEs. Compared with other methods, the presented scheme uses the least number of reconfigurations of an FPGA for its LUT testing.

引用

页码：141 / 146

页数：6

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