Generation of surrogate models of Pareto-optimal performance trade-offs of planar inductors

被引：16

作者：

Kotti, M. ^{[1
]}

Gonzalez-Echevarria, R. ^{[2
,3
]}

Fernandez, F. V. ^{[2
,3
]}

Roca, E. ^{[2
,3
]}

Sieiro, J. ^{[4
]}

Castro-Lopez, R. ^{[2
,3
]}

Fakhfakh, M. ^{[1
]}

Lopez-Villegas, J. M. ^{[4
]}

机构：

[1] Univ Sfax, Sfax, Tunisia

[2] CSIC, Inst Microelect Seville IMSE CNM, Seville 41092, Spain

[3] Univ Seville, Seville 41092, Spain

[4] Univ Barcelona, Fac Fis, Grp Radiofrequencia, E-08028 Barcelona, Spain

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2014年 / 78卷 / 01期

关键词：

RF circuit design; Integrated planar inductors; Performance modeling; Multi-objective optimization; Surrogate modeling; MONTE-CARLO; DESIGN; OPTIMIZATION; EFFICIENT; ALGORITHM;

D O I：

10.1007/s10470-013-0230-8

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Systematic design methodologies for wireless transceivers require an efficient design of integrated inductors. Early availability of feasible trade-offs between inductance, quality factor, self-resonance frequency and area, is a key enabler towards the improvement of such design methodologies. This paper introduces such an approach in two steps. First, a Pareto-optimal performance front of integrated inductors is generated by embedding a performance evaluator into a multi-objective optimization tool. Then, starting from the optimal front samples, a surrogate model of the performance front is obtained. Experimental results in a 0.35-mu m CMOS technology are provided.

引用

页码：87 / 97

页数：11

共 22 条

[1]

[Anonymous], 2011, VIRT PAR CELL REF

[2]

[Anonymous], 2011, CAD SKILL LANG REF

[3] Parasitic-aware design and optimization of a CMOS RF power amplifier [J].