Design and Implementation of IIR Lattice Filter using Floating Point Arithmetic In FPGA

The floating point arithmetic process is the common operation in numerous processors. The floating point adder process is the complex operation as compared to the multiplication as it consists of latency, area dependent sub operations.. The floating point adder is implemented using Leading One Detector (LOD). This technique improves the performance of the adder in terms of area, delay and speed of operation. The multiplication of two floating point numbers is also important in Digital Signal Processing and it is implemented by using generic multiplier. To keep all design properties in an unlocked state, we kept design goal strategies in a balanced mode so that area, delay and speed are always balanced. The digital filter structure is implemented by suing basic building blocks i.e. adders, multipliers and delays. The floating point arithmetic in single precision format and double precision format are used to design IIR lattice filter structure. The aim of this paper is to analyze the different hardware modules used for the implementation of floating point adder and multiplier algorithm using Very high speed integrated circuit Hardware Description Language (VHDL) and implemented on Xilinx Virtex-5 XC5VLX50T device using Xilinx integrated software environment 14.2.