A study of the mechanisms causing surface defects on sidewalls during Si etching for TSV (through Si via)

被引:15
作者
Choi, Jae Woong [1 ]
Loh, Woon Leng [1 ]
Praveen, Sampath Kumar [1 ]
Murphy, Ramana [1 ]
Swee, Eugene Tan Kiat [1 ]
机构
[1] ASTAR, Inst Microelect, Singapore 117685, Singapore
关键词
HIGH-ASPECT-RATIO; SILICON;
D O I
10.1088/0960-1317/23/6/065005
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper we report three mechanisms causing surface defects on Si sidewalls during Si etching for TSV. The first mechanism causing surface defects was a downward surface-defect formation due to the participation of the residual polymerizing gas in the transition periods between passivation steps and etch steps. The second mechanism was an upward surface-defect formation due to etchant attacking the interface between the Si and the sidewall polymer. Although the sidewall polymer was thick enough to protect the Si surface, it was not possible to avoid surface defects if the etch step was not switched to the following passivation step in time. The third mechanism was a sponge-like surface-defect formation caused by either poor polymer depositions or voids inside the sidewall polymer. The sponge-like surface defects were formed by Si isotropic etching through the weak points of the sidewall polymer. All three surface defects were considered as the major factors on TSV integration and packaging reliability issues.
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页数:7
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